A number of different types of locked loop circuits are used in conventional integrated circuits, the two most notable being delay lock loops and phase lock loops. Both of these types of locked loops use a phase detector to compare the phase of a reference clock signal to the phase of a feedback clock signal generated by the locked loop. A phase error signal generated from the comparison is applied to a controller (i.e., a combination of a charge pump and a bias generator) which, in turn, generates an appropriate control signal(s) that is applied to a variable delay line in the case of a delay lock loop or a voltage controlled oscillator in the case of a phase lock loop.
A typical prior art delay lock loop 10 is shown in FIG. 1. The delay lock loop 10 includes a phase detector 12 having a first input receiving a reference clock signal Clk_ref and a second input receiving a feedback clock signal Clk_fb, which is generated from an output clock signal Clk_out. The phase detector 12 generates an UP signal in response to a phase error in one direction, and it generates a DN signal in response to a phase error in the opposite direction. These UP and DN signals are applied to a charge pump 16, which provides a control voltage Vct across a capacitance, such as capacitor 18. As explained in greater detail below, the charge pump 16 also receives a feedback voltage Vfb, which attempts to maintain the rate of charge of the capacitor 18 equal to the rate of discharge. In response to the UP signal, the charge pump 16 charges the capacitor 18 to increase the control voltage Vct, and, in response to the DN signal, the charge pump 16 discharges the capacitor 18 to decrease the control voltage Vct.
The control voltage Vct is applied to a bias generator 20 that generates two bias voltages Vbp, Vbn as a function of the magnitude of the control voltage Vet. These bias voltages Vbp, Vbn control the delay of a voltage controlled delay line 24 as the reference clock signal Clk_ref is coupled through the delay line 24 to generate the output clock signal Clk_out.
There is therefore a need for an improved bias generator operating with a charge pump in a locked loop, such as one that ensures a more even balance between the charge current and the discharge current of the charge pump.